FPGA Resource Estimation for Loop Controllers

High-level synthesis overcomes the high design effort required by using an FPGA by moving the hardware design to a higher abstraction level. At this higher level, loop transformations are used to improve the characteristics of the program. These transformations have a large impact on the resulting hardware, but their impact is only known after the time-consuming synthesis steps. This hinders a fast design space exploration. In this paper, we tackle this issue by estimating the performance of the hardware loop controller, an often overlooked component in other approaches. We present an equation based model to estimate the area and clock frequency of the loop controller during high-level synthesis. In our approach, we manage to keep estimation errors reasonably low, so our estimation model can be used during design space exploration. Due to its simplicity, the overhead is minimal, which is critical when lots of design variants need to be estimated.